I'm about to submit my board for fab, and would appreciate input on how to make it better. I have one 50MHz clock, several 5MHz clocks, and many 2.5MHz signals. I've gone to SMD components (even 0603 size - I hope it's as easy as I'm told) other than RJ45 jacks.
1) I have tried to maximize signal integrity by maximizing ground plane by filling (copper pour) both sides aggressively. Is there any downside to this?
2) In some cases I dropped an "orphan" via in an area that wasn't filled (on one side), added it to the GND net (the other side is GND) and the pour then covers both board sides, including the empty "island". Is there any reason not to do this?
3) I noticed that on terminals on the GND net, after copper pour I see thermal relief as expected, but the traces I had to connect the terminals to the GND added more copper. I realize that (in KiCad - but this didn't seem to work with DesignSparkPCB) I don't have connect all the GND nets together if the copper pour covers the terminal. I've removed all the GND traces from my design where this was the case. I can then add copper fill and run DRC to make sure there are no unconnected GND terminals. Is there any downside to this? (Is this what is normal and/or accepted best practice, I just didn't figure it out initially - or a bad idea?)
I'd like to post the board layout for others to review. What's the best way to do this? Individual Gerber files for each layer give full detail without one layer obscuring the other, but it's harder to see how the whole board connects. With copper pour or without? Would the silk/mask layers also help?
Thanks.
Edit: Added PDFs since Gerber (*.gbr) files would not upload. Separate Front & Back Copper (w/pour) and all layers w/out pour.
Edit: I should add that design grid is 0.025", signal traces are 6/6 and power is 32/6. Default (signal) vias are 10mil drill and 5 mil annular ring, power vias are 16mil drill and 8mil annular ring. All SMD on bottom, and 2 SMD LEDs on top (for obvious reasons) as well as THT RJ45 jacks and 0.1" headers.
1) I have tried to maximize signal integrity by maximizing ground plane by filling (copper pour) both sides aggressively. Is there any downside to this?
2) In some cases I dropped an "orphan" via in an area that wasn't filled (on one side), added it to the GND net (the other side is GND) and the pour then covers both board sides, including the empty "island". Is there any reason not to do this?
3) I noticed that on terminals on the GND net, after copper pour I see thermal relief as expected, but the traces I had to connect the terminals to the GND added more copper. I realize that (in KiCad - but this didn't seem to work with DesignSparkPCB) I don't have connect all the GND nets together if the copper pour covers the terminal. I've removed all the GND traces from my design where this was the case. I can then add copper fill and run DRC to make sure there are no unconnected GND terminals. Is there any downside to this? (Is this what is normal and/or accepted best practice, I just didn't figure it out initially - or a bad idea?)
I'd like to post the board layout for others to review. What's the best way to do this? Individual Gerber files for each layer give full detail without one layer obscuring the other, but it's harder to see how the whole board connects. With copper pour or without? Would the silk/mask layers also help?
Thanks.
Edit: Added PDFs since Gerber (*.gbr) files would not upload. Separate Front & Back Copper (w/pour) and all layers w/out pour.
Edit: I should add that design grid is 0.025", signal traces are 6/6 and power is 32/6. Default (signal) vias are 10mil drill and 5 mil annular ring, power vias are 16mil drill and 8mil annular ring. All SMD on bottom, and 2 SMD LEDs on top (for obvious reasons) as well as THT RJ45 jacks and 0.1" headers.
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