W5500 driver

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DynamoBen

Super Moderator
I'm working on getting some samples of the W5500 from wiznet. The improvement over the W5100 and W5200 is the LQFP package so its easier to solder by hand. Also the module includes hardware for a MAC address which I suspect is the either the microchip part I've been using or a uC of some short.

Once I have samples I will sort out the driver, a quick pass on the datasheet indicates its almost identical to the W5200.
 
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Just heard back from Wiznet and it looks like I won't be able to get samples, but the new module will be available for purchase on Oct 14. I'm asking them about the differences between the W5500 and the W5200. I also got a mailer from Saelig this is what they had to say about it.

WIZnet has just introduced the W5500 Fast SPI Ethernet Controller IC, with enhancements and cost reductions over previous WIZnet Ethernet ICs. The W5500 chip is a hardwired TCP/IP Ethernet controller that provides easy Internet connection to embedded systems by using a single chip in which the TCP/IP stack, 10/100 Ethernet MAC and PHY are embedded. The W5500's TCP/IP Core is composed of a fully-hardwired, market-proven 10BaseT/100BaseTX TCP/IP stack with an integrated Ethernet MAC & PHY which supports TCP, UDP, IPv4, ICMP,ARP, IGMP, and PPPoE protocols. The W5500 now offers a fast, versatile SPI interface (up to 80 MHz) and the ability for a host MCU to flexibly utilize the W5500's buffer RAM for general-purpose data, a plus when using low-cost MCUs with limited on-chip RAM. Product hardware design is also simplified by the reduction of external power supply components and the use of firmware-setting (rather than pin-setting) of physical layer PHY options.
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I saw this pop up on WizNet's site about a month ago. They also have a *IO version of it too, but its not pin compatible with the 820IO. Link. I sent the links off to Jim when I found it and he noticed its got a faster SPI bus.
 
Looks like it's still limited to 8 sockets although if you using unicast you can have 8, 12, 16 or more while only using a single socket so I guess it not a big deal.
 
There are 2 extra chips on the module. The larger one has to be a small micro, the other, I can't tell from the pic if it's an IC or just a large discrete component. I'm guessing it's the mac chip. Apparently the hardware reset line, when de-asserted, causes the on-board micro to come to life, read the mac chip and then communicate with the 5500 to load the mac address, default IP address, etc, then it is done. I'm assuming that that on-board micro is relying on the connected hardware to not attempt to talk to the W5500 during that time, using the READY signal to know when that init is done. Apparently this is a one-time only event that happens when the hardware rest pin is asserted.



It does look like the 5500 needs fewer discrete components. The module form factor is a bit bloated though, given the extra chips, apparently no bottom-mounted components, and the separate transformer instead of a mag-jack. It does bring back the mounting holes.
 
No auto-MDIX, strange. The 3rd chip is an 8-pin device. Also 2 specs for the SPI clock frequency: 80 MHz "theoretical design" and 33mhz "guaranteed minimum".
 
Too bad about no auto MDIX but since most switches and computers have it it's not a great loss.

Personally since the chip is easy to solder I'd just put the chip and a MagJack on the PCB and forget the module.
 
Still requires a lot of discrete components. 20+ resistors, 20+ caps, crystal, inductor, transformer. The transformer used in the 550IO is pricey. Wiznet's reference design varies somewhat from the transformer manufacturers data sheet also. A neat project might be a 5500-based pin-compatible replacement for the WIZ820IO.
 
Finally heard back from wiznet today about the differences between the W5200 and new W5500. See attachment.
 

Attachments

  • W5200_vs_W5500.pdf
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jstjohnz said:
I'm not sure I understand the new SPI protocol.
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Yeah I'm trying to wrap my head around the "Block Select Bit" portion. It seems that its just a shortcut to get to the registers for a given socket. So I think the deal is you select the Block [socket] then you offset into memory for the register you want.
 
jstjohnz said:
How do you control the transfer size? Just stop sending clocks when done?
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Seems like there are two options, fixed and variable. For variable it knows to stop when the chip select pin state changes.

And is the bit order reversed?
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That seems to be true.

Ugh I wish they would stop reinventing the wheel every time they release.
 
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Does somebody have a working W5500 driver (or maybe working spi read/write functions)? Im trying to get a webserver with W5500 working. Im also using an atxmega128a1 for that.
 
I have a working W5500 server for MSP430. With few small changes, it can be used on other platforms.
 
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